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DRV8824 slvsa06i ? october 2009 ? revised june 2014 DRV8824 stepper motor controller ic 1 features 3 description the DRV8824 provides an integrated motor driver 1 ? pwm microstepping stepper motor driver solution for printers, scanners, and other automated ? built-in microstepping indexer equipment applications. the device has two h-bridge ? up to 1/32 microstepping drivers and a microstepping indexer, and is intended to drive a bipolar stepper motor. the output driver ? multiple decay modes: block consists of n-channel power mosfets ? mixed decay configured as full h-bridges to drive the motor ? slow decay windings. the DRV8824 is capable of driving up to 1.6 a of current from each output (with proper ? fast decay heatsinking, at 24 v and 25 c). ? 8.2-v to 45-v operating supply voltage range a simple step/dir interface allows easy interfacing ? 1.6-a maximum drive current at 24 v and to controller circuits. mode pins allow for configuration t a = 25 c of the motor in full-step up to 1/32-step modes. decay ? simple step/dir interface mode is configurable so that slow decay, fast decay, ? low-current sleep mode or mixed decay can be used. a low-power sleep mode is provided which shuts down internal circuitry ? built-in 3.3-v reference output to achieve very-low quiescent current draw. this ? small package and footprint sleep mode can be set using a dedicated nsleep ? protection features: pin. ? overcurrent protection (ocp) internal shutdown functions are provided for ? thermal shutdown (tsd) overcurrent, short circuit, undervoltage lockout, and over temperature. fault conditions are indicated ? vm undervoltage lockout (uvlo) through the nfault pin. ? fault condition indication pin (nfault) device information (1) 2 applications part number package body size (nom) ? automatic teller machines htssop (28) 9.70 mm 6.40 mm DRV8824 ? money handling machines qfn (28) 5.00 mm 5.00 mm ? video security cameras (1) for all available packages, see the orderable addendum at the end of the data sheet. ? printers ? scanners ? office automation machines ? gaming machines ? factory automation ? robotics 4 simplified schematic microstepping current waveform 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. current (% of full scale) electrical angle increasing current decreasing current increasing current decreasing current step step size decay mode 8.2 to 45 v controller m + + DRV8824 1/32 step stepper motor driver 1.6 a 1.6 a dir nfault productfolder sample &buy technical documents tools & software support &community
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com table of contents 8.3 feature description ................................................. 11 1 features .................................................................. 1 8.4 device functional modes ........................................ 18 2 applications ........................................................... 1 9 application and implementation ........................ 19 3 description ............................................................. 1 9.1 application information ............................................ 19 4 simplified schematic ............................................. 1 9.2 typical application .................................................. 19 5 revision history ..................................................... 2 10 power supply recommendations ..................... 22 6 pin configuration and functions ......................... 3 10.1 bulk capacitance .................................................. 22 7 specifications ......................................................... 4 10.2 power supply and logic sequencing ................... 22 7.1 absolute maximum ratings ...................................... 4 11 layout ................................................................... 23 7.2 handling ratings ....................................................... 4 11.1 layout guidelines ................................................. 23 7.3 recommended operating conditions ....................... 4 11.2 layout example .................................................... 23 7.4 thermal information .................................................. 5 12 device and documentation support ................. 24 7.5 electrical characteristics ........................................... 6 12.1 trademarks ........................................................... 24 7.6 timing requirements ................................................ 7 12.2 electrostatic discharge caution ............................ 24 7.7 typical characteristics .............................................. 8 12.3 glossary ................................................................ 24 8 detailed description .............................................. 9 13 mechanical, packaging, and orderable 8.1 overview ................................................................... 9 information ........................................................... 24 8.2 functional block diagram ....................................... 10 5 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision h (december 2013) to revision i page ? updated data sheet to new ti standard: added sections and rearranged material .............................................................. 1 ? updated pin description for avref and bvref .................................................................................................................. 3 ? added power supply ramp rate to absolute maximum ratings ............................................................................................ 4 ? added minimum voltage for v il and removed typical ............................................................................................................. 6 ? updated parameter descriptions in timing requirements and t wake minimum and maximum ............................................. 7 changes from revision g (august 2013) to revision h page ? changed in electrical characteristics table, section decay input third row ...................................................................... 6 2 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 6 pin configuration and functions pwp package rhd package (top view) (top view) pin functions pin i/o (1) description external components or connections name pwp rhd power and ground gnd 14, 28 3, 17 ? device ground vma 4 7 ? bridge a power supply connect to motor supply (8.2 to 45 v). both pins must be connected to same supply, bypassed with a 0.1- f capacitor to gnd, and connected vmb 11 14 ? bridge b power supply to appropriate bulk capacitance. bypass to gnd with a 0.47- f 6.3-v ceramic capacitor. can be used to v3p3out 15 18 o 3.3-v regulator output supply vref. cp1 1 4 io charge pump flying capacitor connect a 0.01- f 50-v capacitor between cp1 and cp2. cp2 2 5 io charge pump flying capacitor vcp 3 6 io high-side gate drive voltage connect a 0.1- f 16-v ceramic capacitor and a 1-m resistor to vm. control logic high to disable device outputs and indexer operation, logic low to nenbl 21 24 i enable input enable. internal pulldown. logic high to enable device, logic low to enter low-power sleep mode. nsleep 17 20 i sleep mode input internal pulldown. step 22 25 i step input rising edge causes the indexer to move one step. internal pulldown. dir 20 23 i direction input level sets the direction of stepping. internal pulldown. mode0 24 27 i microstep mode 0 mode0 through mode2 set the step mode: full, 1/2, 1/4, 1/8/ 1/16, or mode1 25 28 i microstep mode 1 1/32 step. internal pulldown. mode2 26 1 i microstep mode 2 low = slow decay, open = mixed decay, decay 19 22 i decay mode high = fast decay. internal pulldown and pullup. active-low reset input initializes the indexer logic and disables the h- nreset 16 19 i reset input bridge outputs. internal pulldown. bridge a current set reference avref 12 15 i input reference voltage for winding current set. normally avref and bvref are connected to the same voltage. can be connected to v3p3out. bridge b current set reference bvref 13 16 i input nc 23 26 ? no connect leave this pin unconnected. (1) directions: i = input, o = output, od = open-drain output, io = input/output copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: DRV8824 isena 1 2 3 4 5 6 7 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 gnd (ppad) mode2 nhome gnd cp1cp2 vcp vma nfault nsleep nreset v3p3out gndbvref avref vmb bout 1 isenb bout 2 aout 2 aout 2 decay dir nenbl step nc mode 0 mode 1
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com pin functions (continued) pin i/o (1) description external components or connections name pwp rhd status nhome 27 2 od home position logic low when at home state of step table nfault 18 21 od fault logic low when in fault condition (overtemperature, overcurrent) output isena 6 9 io bridge a ground / isense connect to current sense resistor for bridge a. isenb 9 12 io bridge b ground / isense connect to current sense resistor for bridge b. aout1 5 8 o bridge a output 1 connect to bipolar stepper motor winding a. positive current is aout1 aout2 aout2 7 10 o bridge a output 2 bout1 10 13 o bridge b output 1 connect to bipolar stepper motor winding b. positive current is bout1 bout2 bout2 8 11 o bridge b output 2 7 specifications 7.1 absolute maximum ratings over operating free-air temperature (unless otherwise noted) (1) (2) min max unit vmx power supply voltage ? 0.3 47 v vmx power supply ramp rate 1 v/ s digital pin voltage ? 0.5 7 v vref input voltage ? 0.3 4 v isensex pin voltage (3) ? 0.8 0.8 v peak motor drive output current, t < 1 s internally limited a continuous motor drive output current (4) 1.6 a continuous total power dissipation see thermal information t j operating virtual junction temperature range ? 40 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground pin. (3) transients of 1 v for less than 25 ns are acceptable. (4) power dissipation and thermal limits must be observed. 7.2 handling ratings min max unit t stg storage temperature range ? 60 150 c human body model (hbm), per ansi/esda/jedec js-001, all pins (1) ? 2000 2000 electrostatic v (esd) v discharge charged device model (cdm), per jedec specification jesd22-c101, all pins (2) ? 500 500 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.3 recommended operating conditions min nom max unit v m motor power supply voltage range (1) 8.2 45 v v ref vref input voltage (2) 1 3.5 v i v3p3 v3p3out load current 1 ma (1) all v m pins must be connected to the same supply voltage. (2) operational at vref between 0 and 1 v, but accuracy is degraded. 4 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 7.4 thermal information DRV8824 thermal metric unit pwp (28 pins) rhd (28 pins) r ja junction-to-ambient thermal resistance (1) 38.9 35.8 r jc(top) junction-to-case (top) thermal resistance (2) 23.3 25.1 r jb junction-to-board thermal resistance (3) 21.2 8.2 c/w jt junction-to-top characterization parameter (4) 0.8 0.3 jb junction-to-board characterization parameter (5) 20.9 8.2 r jc(bot) junction-to-case (bottom) thermal resistance (6) 2.6 1.1 (1) the junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a jedec-standard, high-k board, as specified in jesd51-7, in an environment described in jesd51-2a. (2) the junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. no specific jedec- standard test exists, but a close description can be found in the ansi semi standard g30-88. (3) the junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. (4) the junction-to-top characterization parameter, jt , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (5) the junction-to-board characterization parameter, jb , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (6) the junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. no specific jedec standard test exists, but a close description can be found in the ansi semi standard g30-88. spacer copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: DRV8824
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com 7.5 electrical characteristics over operating free-air temperature range of ? 40 c to 85 c (unless otherwise noted) parameter test conditions min typ max unit power supplies i vm vm operating supply current v m = 24 v, f pwm < 50 khz 5 8 ma i vmq vm sleep mode supply current v m = 24 v 10 20 a v3p3out regulator iout = 0 to 1 ma, v m = 24 v, t j = 25 c 3.18 3.30 3.42 v 3p3 v3p3out voltage v iout = 0 to 1 ma 3.10 3.30 3.50 logic-level inputs v il input low voltage 0 0.7 v v ih input high voltage 2 5.25 v v hys input hysteresis 0.45 v i il input low current vin = 0 ? 20 20 a i ih input high current vin = 3.3 v 100 a nenbl, nreset, dir, step, modex 100 k r pd internal pulldown resistance nsleep 1 m nhome, nfault outputs (open-drain outputs) v ol output low voltage i o = 5 ma 0.5 v i oh output high leakage current v o = 3.3 v 1 a decay input v il input low threshold voltage for slow decay mode 0.8 v v ih input high threshold voltage for fast decay mode 2 v i in input current ? 100 100 a r pu internal pullup resistance 130 k r pd internal pulldown resistance 80 k h-bridge fets v m = 24 v, i o = 1 a, t j = 25 c 0.63 r ds(on) hs fet on resistance ? v m = 24 v, i o = 1 a, t j = 85 c 0.76 0.90 v m = 24 v, i o = 1 a, t j = 25 c 0.65 r ds(on) ls fet on resistance ? v m = 24 v, i o = 1 a, t j = 85 c 0.78 0.90 i off off-state leakage current ? 20 20 a motor driver ? pwm internal pwm frequency 50 khz t blank current sense blanking time 3.75 s t r rise time v m = 24 v 100 360 ns t f fall time v m = 24 v 80 250 ns t dead dead time 400 ns protection circuits v uvlo vm undervoltage lockout voltage v m rising 7.8 8.2 v i ocp overcurrent protection trip level 1.8 5 a t deg overcurrent deglitch time 1.75 s t tsd thermal shutdown temperature die temperature 150 160 180 c current control i ref xvref input current xvref = 3.3 v ? 3 3 a v trip xisense trip voltage xvref = 3.3 v, 100% current setting 635 660 685 mv 6 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 electrical characteristics (continued) over operating free-air temperature range of ? 40 c to 85 c (unless otherwise noted) parameter test conditions min typ max unit xvref = 3.3 v , 5% current setting ? 25% 25% xvref = 3.3 v , 10% to 34% current setting ? 15% 15% current trip accuracy i trip (relative to programmed value) xvref = 3.3 v, 38% to 67% current setting ? 10% 10% xvref = 3.3 v, 71% to 100% current setting ? 5% 5% a isense current sense amplifier gain reference only 5 v/v 7.6 timing requirements min max unit 1 ? step step frequency 250 khz 2 t wh(step) pulse duration, step high 1.9 s 3 t wl(step) pulse duration, step low 1.9 s 4 t su(step) setup time, command before step rising 200 ns 5 t h(step) hold time, command after step rising 200 ns 6 t enbl enable time, nenbl active to step 200 ns 7 t wake wakeup time, nsleep inactive high to step input accepted 1 ms figure 1. timing diagram copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: DRV8824
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com 7.7 typical characteristics figure 2. i vm vs vm figure 3. i vmq vs vm figure 4. r ds(on) vs vm figure 5. r ds(on) vs temperature 8 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824 800 1000 1200 1400 1600 1800 2000 10 15 20 25 30 35 40 45 r ds(on) hs + ls (m ? ) vm (v) -40c 25c 85c 125c c003 800 1000 1200 1400 1600 1800 2000 50 25 0 25 50 75 100 125 r ds(on) hs + ls (m ? ) t a ( ? c) 10 v 24 v 45 v c004 4.0 4.5 5.0 5.5 6.0 6.5 7.0 10 15 20 25 30 35 40 45 i vm (ma) vm (v) 25c 85c 125c c001 6 7 8 9 10 11 12 13 14 10 15 20 25 30 35 40 45 i vmq ( a) vm (v) -40c 25c 85c 125c c002
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 8 detailed description 8.1 overview the DRV8824 is an integrated motor driver solution for bipolar stepper motors. the device integrates two nmos h-bridges, current sense, regulation circuitry, and a microstepping indexer. the DRV8824 can be powered with a supply voltage between 8.2 to 45 v and is capable of providing an output current up to 1.6 a full-scale. a simple step/dir interface allows for easy interfacing to the controller circuit. the internal indexer is able to execute high-accuracy microstepping without requiring the processor to control the current level. the current regulation is highly configurable, with three decay modes of operation. fast, slow, and mixed decay can be selected depending on the application requirements. a low-power sleep mode is included which allows the system to save power when not driving the motor. copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: DRV8824
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com 8.2 functional block diagram 10 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824 gnd gnd ppad nfault nhome nsleep nreset mode2 mode1 mode0 dir step nenbl control logic/ indexer decay internal vcc low side gate drive v3p3out bvref avref 3.3 v 3.3 v v3p3out thermal shut down motor driver b motor driver a charge pump isenb bout2 bout1 vmb isena aout2 aout1 vma vcp cp2 cp1 vm vm vm hs gate drive ls gate drive vm vm + + stepper motor +
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 8.3 feature description 8.3.1 pwm motor drivers the DRV8824 contains two h-bridge motor drivers with current-control pwm circuitry. figure 6 shows a block diagram of the motor control circuitry. figure 6. motor control circuitry note that there are multiple vm motor power supply pins. all vm pins must be connected together to the motor supply voltage. copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: DRV8824
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com feature description (continued) 8.3.2 current regulation the current through the motor windings is regulated by a fixed-frequency pwm current regulation, or current chopping. when an h-bridge is enabled, current rises through the winding at a rate dependent on the dc voltage and inductance of the winding. after the current hits the current chopping threshold, the bridge disables the current until the beginning of the next pwm cycle. in stepping motors, current regulation is used to vary the current in the two windings in a semi-sinusoidal fashion to provide smooth motion. the pwm chopping current is set by a comparator which compares the voltage across a current sense resistor connected to the xisen pins, multiplied by a factor of 5, with a reference voltage. the reference voltage is input from the xvref pins. the full-scale (100%) chopping current is calculated in equation 1 . (1) example: if a 0.5- ? sense resistor is used and the vrefx pin is 3.3 v, the full-scale (100%) chopping current will be 3.3 v / (5 0.5 ? ) = 1.32 a. the reference voltage is scaled by an internal dac that allows fractional stepping of a bipolar stepper motor, as described in microstepping indexer . 8.3.3 decay mode during pwm current chopping, the h-bridge is enabled to drive current through the motor winding until the pwm current chopping threshold is reached. figure 7 shows this as case 1. the current flow direction shown indicates positive current flow. after the chopping current threshold is reached, the h-bridge can operate in two different states, fast decay or slow decay. in fast decay mode, after the pwm chopping current level has been reached, the h-bridge reverses state to allow winding current to flow in a reverse direction. as the winding current approaches 0, the bridge is disabled to prevent any reverse current flow. figure 7 shows fast decay mode as case 2. in slow decay mode, winding current is re-circulated by enabling both of the low-side fets in the bridge. figure 7 shows this as case 3. 12 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824 i = chop v refx 5 r isense ?
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 feature description (continued) figure 7. decay mode the DRV8824 supports fast decay, slow decay, and a mixed decay mode. slow, fast, or mixed decay mode is selected by the state of the decay pin ? logic low selects slow decay, open selects mixed decay operation, and logic high sets fast decay mode. the decay pin has both an internal pullup resistor of approximately 130 k and an internal pulldown resistor of approximately 80 k . this sets the mixed decay mode if the pin is left open or undriven. mixed decay mode begins as fast decay, but at a fixed period of time (75% of the pwm cycle) switches to slow decay mode for the remainder of the fixed pwm period. this occurs only if the current through the winding is decreasing (per table 2 ); if the current is increasing, then slow decay is used. 8.3.4 blanking time after the current is enabled in an h-bridge, the voltage on the xisen pin is ignored for a fixed period of time before enabling the current sense circuitry. this blanking time is fixed at 3.75 s. note that the blanking time also sets the minimum on time of the pwm. 8.3.5 microstepping indexer built-in indexer logic in the DRV8824 allows a number of different stepping configurations. the mode0 through mode2 pins are used to configure the stepping format, as shown in table 1 . table 1. stepping format mode2 mode1 mode0 step mode 0 0 0 full step (2-phase excitation) with 71% current 0 0 1 1/2 step (1-2 phase excitation) 0 1 0 1/4 step (w1-2 phase excitation) 0 1 1 8 microsteps/step 1 0 0 16 microsteps/step 1 0 1 32 microsteps/step 1 1 0 32 microsteps/step 1 1 1 32 microsteps/step copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: DRV8824
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com table 2 shows the relative current and step directions for different settings of modex. at each rising edge of the step input, the indexer travels to the next state in the table. the direction is shown with the dir pin high; if the dir pin is low, the sequence is reversed. positive current is defined as xout1 = positive with respect to xout2. note that if the step mode is changed while stepping, the indexer advances to the next valid state for the new modex setting at the rising edge of step. the home state is 45 . this state is entered at power-up or application of nreset. this is shown in table 2 by the shaded cells. the logic inputs dir, step, nreset, and modex have an internal pulldown resistors of 100 k table 2. relative current and step directions 1/32 1/16 1/8 1/4 1/2 full step winding current winding current electrical step step step step step 70% a b angle 1 1 1 1 1 100% 0% 0 2 100% 5% 3 3 2 100% 10% 6 4 99% 15% 8 5 3 2 98% 20% 11 6 97% 24% 14 7 4 96% 29% 17 8 94% 34% 20 9 5 3 2 92% 38% 23 10 90% 43% 25 11 6 88% 47% 28 12 86% 51% 31 13 7 4 83% 56% 34 14 80% 60% 37 15 8 77% 63% 39 16 74% 67% 42 17 9 5 3 2 1 71% 71% 45 18 67% 74% 48 19 10 63% 77% 51 20 60% 80% 53 21 11 6 56% 83% 56 22 51% 86% 59 23 12 47% 88% 62 24 43% 90% 65 25 13 7 4 38% 92% 68 26 34% 94% 70 27 14 29% 96% 73 28 24% 97% 76 29 15 8 20% 98% 79 30 15% 99% 82 31 16 10% 100% 84 32 5% 100% 87 33 17 9 5 3 0% 100% 90 34 ? 5% 100% 93 35 18 ? 10% 100% 96 36 ? 15% 99% 98 37 19 10 ? 20% 98% 101 38 ? 24% 97% 104 14 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 table 2. relative current and step directions (continued) 1/32 1/16 1/8 1/4 1/2 full step winding current winding current electrical step step step step step 70% a b angle 39 20 ? 29% 96% 107 40 ? 34% 94% 110 41 21 11 6 ? 38% 92% 113 42 ? 43% 90% 115 43 22 ? 47% 88% 118 44 ? 51% 86% 121 45 23 12 ? 56% 83% 124 46 ? 60% 80% 127 47 24 ? 63% 77% 129 48 ? 67% 74% 132 49 25 13 7 4 2 ? 71% 71% 135 50 ? 74% 67% 138 51 26 ? 77% 63% 141 52 ? 80% 60% 143 53 27 14 ? 83% 56% 146 54 ? 86% 51% 149 55 28 ? 88% 47% 152 56 ? 90% 43% 155 57 29 15 8 ? 92% 38% 158 58 ? 94% 34% 160 59 30 ? 96% 29% 163 60 ? 97% 24% 166 61 31 16 ? 98% 20% 169 62 ? 99% 15% 172 63 32 ? 100% 10% 174 64 ? 100% 5% 177 65 33 17 9 5 ? 100% 0% 180 66 ? 100% ? 5% 183 67 34 ? 100% ? 10% 186 68 ? 99% ? 15% 188 69 35 18 ? 98% ? 20% 191 70 ? 97% ? 24% 194 71 36 ? 96% ? 29% 197 72 ? 94% ? 34% 200 73 37 19 10 ? 92% ? 38% 203 74 ? 90% ? 43% 205 75 38 ? 88% ? 47% 208 76 ? 86% ? 51% 211 77 39 20 ? 83% ? 56% 214 78 ? 80% ? 60% 217 79 40 ? 77% ? 63% 219 80 ? 74% ? 67% 222 81 41 21 11 6 3 ? 71% ? 71% 225 82 ? 67% ? 74% 228 83 42 ? 63% ? 77% 231 84 ? 60% ? 80% 233 85 43 22 ? 56% ? 83% 236 copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: DRV8824
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com table 2. relative current and step directions (continued) 1/32 1/16 1/8 1/4 1/2 full step winding current winding current electrical step step step step step 70% a b angle 86 ? 51% ? 86% 239 87 44 ? 47% ? 88% 242 88 ? 43% ? 90% 245 89 45 23 12 ? 38% ? 92% 248 90 ? 34% ? 94% 250 91 46 ? 29% ? 96% 253 92 ? 24% ? 97% 256 93 47 24 ? 20% ? 98% 259 94 ? 15% ? 99% 262 95 48 ? 10% ? 100% 264 96 ? 5% ? 100% 267 97 49 25 13 7 0% ? 100% 270 98 5% ? 100% 273 99 50 10% ? 100% 276 100 15% ? 99% 278 101 51 26 20% ? 98% 281 102 24% ? 97% 284 103 52 29% ? 96% 287 104 34% ? 94% 290 105 53 27 14 38% ? 92% 293 106 43% ? 90% 295 107 54 47% ? 88% 298 108 51% ? 86% 301 109 55 28 56% ? 83% 304 110 60% ? 80% 307 111 56 63% ? 77% 309 112 67% ? 74% 312 113 57 29 15 8 4 71% ? 71% 315 114 74% ? 67% 318 115 58 77% ? 63% 321 116 80% ? 60% 323 117 59 30 83% ? 56% 326 118 86% ? 51% 329 119 60 88% ? 47% 332 120 90% ? 43% 335 121 61 31 16 92% ? 38% 338 122 94% ? 34% 340 123 62 96% ? 29% 343 124 97% ? 24% 346 125 63 32 98% ? 20% 349 126 99% ? 15% 352 127 64 100% ? 10% 354 128 100% ? 5% 357 16 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 8.3.6 nreset, nenble and nsleep operation the nreset pin, when driven active low, resets internal logic, and resets the step table to the home position. it also disables the h-bridge drivers. the step input is ignored while nreset is active. the nenbl pin is used to control the output drivers and enable or disable operation of the indexer. when nenbl is low, the output h-bridges are enabled, and rising edges on the step pin are recognized. when nenbl is high, the h-bridges are disabled, the outputs are in a high-impedance state, and the step input is ignored. driving nsleep low puts the device into a low-power sleep state. in this state, the h-bridges are disabled, the gate drive charge pump is stopped, the v3p3out regulator is disabled, and all internal clocks are stopped. in this state, all inputs are ignored until nsleep returns high. when returning from sleep mode, some time (approximately 1 ms) needs to pass before applying a step input, to allow the internal circuitry to stabilize. the nreset and nenable pins have internal pulldown resistors of 100 k . the nsleep pin has an internal pulldown resistor of 1 m . 8.3.7 protection circuits the DRV8824 is fully protected against undervoltage, overcurrent, and overtemperature events. 8.3.7.1 overcurrent protection (ocp) an analog current limit circuit on each fet limits the current through the fet by removing the gate drive. if this analog current limit persists for longer than the ocp time, all fets in the h-bridge will be disabled and the nfault pin will be driven low. the device remains disabled until either nreset pin is applied, or vm is removed and re-applied. overcurrent conditions on both high and low side devices, that is, a short to ground, supply, or across the motor winding, all result in an overcurrent shutdown. note that overcurrent protection does not use the current sense circuitry used for pwm current control, and is independent of the i sense resistor value or vref voltage. 8.3.7.2 thermal shutdown (tsd) if the die temperature exceeds safe limits, all fets in the h-bridge will be disabled and the nfault pin will be driven low. after the die temperature has fallen to a safe level, operation automatically resumes. 8.3.7.3 undervoltage lockout (uvlo) if at any time the voltage on the vm pins falls below the uvlo threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. operation resumes when v m rises above the uvlo threshold. 8.3.8 thermal information 8.3.8.1 thermal protection the DRV8824 has tsd, as described in thermal shutdown (tsd) . if the die temperature exceeds approximately 150 c, the device is disabled until the temperature drops to a safe level. any tendency of the device to enter tsd is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. 8.3.8.2 power dissipation power dissipation in the DRV8824 is dominated by the power dissipated in the output fet resistance, or r ds(on) . average power dissipation when running a stepper motor can be roughly estimated by equation 2 . where ? p tot is the total power dissipation ? r ds(on) is the resistance of each fet ? i out(rms) is the rms output current being applied to each winding (2) copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: DRV8824 p = r (i ) tot ds(on) out(rms) 4 2
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com i out(rms) is equal to the approximately 0.7 the full-scale output current setting. the factor of 4 comes from the fact that there are two motor windings, and at any instant two fets are conducting winding current for each winding (one high-side and one low-side). the maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. note that r ds(on) increases with temperature, so as the device heats, the power dissipation increases. this must be taken into consideration when sizing the heatsink. 8.3.8.3 heatsinking the powerpad ? package uses an exposed pad to remove heat from the device. for proper operation, this pad must be thermally connected to copper on the pcb to dissipate heat. on a multi-layer pcb with a ground plane, this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. on pcbs without internal planes, copper area can be added on either side of the pcb to dissipate heat. if the copper area is on the opposite side of the pcb from the device, thermal vias are used to transfer the heat between top and bottom layers. for details about how to design the pcb, refer to ti application report slma002 , powerpad ? thermally enhanced package and ti application brief slma004 , powerpad ? made easy , available at www.ti.com . in general, the more copper area that can be provided, the more power can be dissipated. it can be seen that the heatsink effectiveness increases rapidly to about 20 cm 2 , then levels off somewhat for larger areas. 8.4 device functional modes 8.4.1 step/dir interface the step/dir interface provides a simple method for advancing through the indexer table. for each rising edge on the step pin, the indexer travels to the next state in the table. the direction it moves in the table is determined by the input to the dir pin. the signals applied to the step and dir pins should not violate the timing diagram specified in figure 1 . 8.4.2 microstepping the microstepping indexer allows for a variety of stepping configurations. the state of the indexer is determined by the configuration of the three mode pins (refer to table 1 for configuration options). the DRV8824 supports full step up to 1/32 microstepping. 18 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 9 application and implementation 9.1 application information the DRV8824 is used in bipolar stepper control. the microstepping motor driver provides additional precision and a smooth rotation from the stepper motor. the following design is a common application of the DRV8824. 9.2 typical application 9.2.1 design requirements table 3 gives design input parameters for system design. table 3. design parameters design parameter reference example value supply voltage vm 24 v motor winding resistance r l 1.0 ? /phase motor winding inductance l l 3.5 mh/phase motor full step angle step 1.8 /step target microstepping level n m 8 microsteps per step target motor speed v 120 rpm target full-scale current i fs 1.25 a copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: DRV8824 gnd nhome mode2 mode1 mode0 nc step nenbl dir decay nfault nsleep nreset v3p3out cp1 cp2 vcp vma aout1 isena aout2 bout2 isenb bout1 vmb avref bvref gnd DRV8824 ppad 0.01 f 0.1 f 400 m ? 400 m ? 1m ? + stepper motor + 0.1 f 0.1 f 100 f vm + 0.47 f v3p3out 10 k ? v3p3out 10 k ? v3p3out v3p3out 10 k ? 30 k ?
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com 9.2.2 detailed design procedure 9.2.2.1 stepper motor speed the first step in configuring the DRV8824 requires the desired motor speed and microstepping level. if the target application requires a constant speed, then a square wave with frequency ? step must be applied to the step pin. if the target motor speed is too high, the motor will not spin. make sure that the motor can support the target speed. for a desired motor speed (v), microstepping level (n m ), and motor full step angle ( step ), (3) step can be found in the stepper motor datasheet or written on the motor itself. for the DRV8824, the microstepping level is set by the usm pins and can be any of the settings in table 1 . higher microstepping will mean a smoother motor motion and less audible noise, but will increase switching losses and require a higher ? step to achieve the same motor speed. 9.2.2.2 current regulation in a stepper motor, the full-scale current (i fs ) is the maximum current driven through either winding. this quantity will depend on the vref analog voltage and the sense resistor value (r sense ). during stepping, i fs defines the current chopping threshold (i trip ) for the maximum current step. (4) i fs is set by a comparator which compares the voltage across r sense to a reference voltage. there is a current sense amplifier built in with programmable gain through isgain. note that i fs must also follow equation 5 in order to avoid saturating the motor. vm is the motor supply voltage and r l is the motor winding resistance. (5) 9.2.2.3 decay modes the DRV8824 supports three different decay modes: slow decay, fast decay, and mixed decay. the current through the motor windings is regulated using a fixed-frequency pwm scheme. this means that after any drive phase, when a motor winding current has hit the current chopping threshold (i trip ), the DRV8824 will place the winding in one of the three decay modes until the pwm cycle has expired. afterward, a new drive phase starts. the blanking time t blank defines the minimum drive time for the current chopping. i trip is ignored during t blank , so the winding current may overshoot the trip level. 20 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824 i (a) = fs vref(v) ? a v r ( ) sense w = vref(v) ? 5 r ( ) sense w f (steps/second) = step v(rpm) n (steps) m 6 ? q step ( /step) i (a) < fs vm(v) ? r ( ) + l w 2 r ( ) + rsense( ) ds(on) w w
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 9.2.3 application curves figure 8. microstepping waveform, phase a, mixed decay figure 9. microstepping waveform, slow decay on increasing steps figure 10. microstepping waveform, mixed decay on decreasing steps copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: DRV8824
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com 10 power supply recommendations the DRV8824 is designed to operate from an input voltage supply (vm) range between 8.2 and 45 v. two 0.01- f ceramic capacitors rated for vm must be placed as close as possible to the vma and vmb pins respectively (one on each pin). in addition to the local decoupling caps, additional bulk capacitance is required and must be sized accordingly to the application requirements. 10.1 bulk capacitance local bulk capacitance sizing is a critical factor in proper motor drive system design. it is dependent on a variety of factors including the type of power supply, inductance in the power supply wiring, type of motor, load demands/dumps of the motor, acceptable voltage ripple, and various other factors. although power supplies often contain large amounts of bulk capacitance, this is often separated from the local motor drive system by parasitic inductance in the power supply wiring. the parasitic inductance will limit the rate current can change from the power supply and force the system to demand or dump current from or to another source with a lower inductance path. this source is often the local bulk capacitance located near the motor drive system. the magnitude and rate of the motor current demand or dump and acceptable voltage ripple will determine how large this bulk capacitance needs to be. the data sheet provides a recommended bulk capacitance value, but system-level testing is required to determine the appropriate sized capacitor for specific applications. a smaller filter capacitor (optional) may also be added to remove higher frequency noise from the power supply lines that may pass the bulk capacitance. figure 11. example setup of motor drive system with external power supply 10.2 power supply and logic sequencing there is no specific sequence for powering-up the DRV8824. it is okay for digital input signals to be present before vm is applied. after vm is applied to the DRV8824, it begins operation based on the status of the control pins. 22 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824 local bulk cap power supply bulk capacitor parasitic wire inductance + motor driver local filter cap external power supply motor drive system vm gnd
DRV8824 www.ti.com slvsa06i ? october 2009 ? revised june 2014 11 layout 11.1 layout guidelines the vma and vmb terminals should be bypassed to gnd using low-esr ceramic bypass capacitors with a recommended value of 0.01 f rated for vm. this capacitor should be placed as close to the vma and vmb pins as possible with a thick trace or ground plane connection to the device gnd pin. the vma and vmb pins must be bypassed to ground using a bulk capacitor. this component may be an electrolytic. if vma and vmb are connected to the same board net, a single bulk capacitor is sufficient. a low-esr ceramic capacitor must be placed in between the cpl and cph pins. ti recommends a value of 0.01 f rated for vma and vmb. place this component as close to the pins as possible. a low-esr ceramic capacitor must be placed in between the vma and vcp pins. ti recommends a value of 0.1 f rated for 16 v. place this component as close to the pins as possible. also, place a 1-m ? resistor between vcp and vma. bypass v3p3 to ground with a ceramic capacitor rated 6.3 v. place this bypassing capacitor as close to the pin as possible. 11.2 layout example copyright ? 2009 ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: DRV8824 0.1 f 0.01 f cp1 gnd cp2 vcp vma aout1 isena aout2 bout2 isenb bout1 vmb avref nhome mode2 mode1 mode0 nc step nembl dir decay nfault nsleep bvref gnd nreset v3p3out 0.47 f 0.1 f 0.1 f + r isena r isenb 1 m ?
DRV8824 slvsa06i ? october 2009 ? revised june 2014 www.ti.com 12 device and documentation support 12.1 trademarks powerpad is a trademark of texas instruments. 12.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 24 submit documentation feedback copyright ? 2009 ? 2014, texas instruments incorporated product folder links: DRV8824
package option addendum www.ti.com 7-apr-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples DRV8824pwp active htssop pwp 28 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 DRV8824 DRV8824pwpr active htssop pwp 28 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 DRV8824 DRV8824rhdr active vqfn rhd 28 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 DRV8824 DRV8824rhdt active vqfn rhd 28 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 DRV8824 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 7-apr-2014 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant DRV8824pwpr htssop pwp 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 DRV8824rhdr vqfn rhd 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 DRV8824rhdt vqfn rhd 28 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 package materials information www.ti.com 7-apr-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) DRV8824pwpr htssop pwp 28 2000 367.0 367.0 38.0 DRV8824rhdr vqfn rhd 28 3000 367.0 367.0 35.0 DRV8824rhdt vqfn rhd 28 250 552.0 154.0 36.0 package materials information www.ti.com 7-apr-2014 pack materials-page 2

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